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Intel Memory Model
In computing, Intel Memory Model refers to a set of six different memory models of the x86 CPU operating in real mode which control how the segment registers are used and the default size of pointers.
== Memory segmentation ==
(詳細はdata segment), CS (code segment), SS (stack segment), and ES (extra segment). Another 16-bit register can act as an offset into a given segment, and so a logical address on this platform is written ''segment'':''offset'', typically in hexadecimal notation. In real mode, in order to calculate the physical address of a byte of memory, the hardware shifts the contents of the appropriate segment register 4 bits left (effectively multiplying by 16), and then adds the offset.
For example, the logical address 7522:F139 yields the 20-bit physical address:
75220 + F139 = 84359
Note that this process leads to aliasing of memory, such that any given physical address may have multiple logical representations. This means that comparison of pointers in different segments is a complicated process.
抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』
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